HD6413008VF25 Datasheet, PDF (277/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the
T₃ state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented.
Figure 8.38 shows the timing in this case.
16TCNT word write cycle
T₁
T₂
T₃
φ
Address bus
16TCNT address
Internal write signal
16TCNT input clock
16TCNT
N
M
16TCNT write data
Figure 8.38 Contention between 16TCNT Word Write and Increment
Rev.4.00 Aug. 20, 2007 Page 231 of 638
REJ09B0395-0400