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HD6413008VF25 Datasheet, PDF (297/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
9. 8-Bit Timers
9.2.4 Timer Control Register (8TCR)
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT
clearing specification, and enables interrupt requests.
8TCR is initialized to H'00 by a reset and in standby mode.
For the timing, see section 9.4, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt
request when the CMFB flag is set to 1 in 8TCSR.
Bit 7
CMIEB
0
1
Description
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
(Initial value)
Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt
request when the CMFA flag is set to 1 in 8TCSR.
Bit 6
CMIEA
0
1
Description
CMIA interrupt requested by CMFA is disabled
CMIA interrupt requested by CMFA is enabled
(Initial value)
Bit 5—Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt
request when the OVF flag is set to 1 in 8TCSR.
Bit 5
OVIE
0
1
Description
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 251 of 638
REJ09B0395-0400