HD6413008VF25 Datasheet, PDF (472/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. A/D Converter
(1)
φ
Address bus (2)
Write signal
Input sampling
timing
ADF
t_D
t _SPL
t _CONV
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t_D : Synchronization delay
t_SPL : Input sampling time
t_CONV : A/D conversion time
Figure 14.5 A/D Conversion Timing
Table 14.4 A/D Conversion Time (Single Mode)
CKS = 0
Symbol
Min
Typ
Max Min
Synchronization delay
t
D
6
⎯
Input sampling time
t_SPL
⎯
31
A/D conversion time
t_CONV
131
⎯
Note: Values in the table are numbers of states.
9
4
⎯
⎯
134 69
CKS = 1
Typ
Max
⎯
5
15
⎯
⎯
70
Rev.4.00 Aug. 20, 2007 Page 426 of 638
REJ09B0395-0400