HD6413008VF25 Datasheet, PDF (365/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

11. Watchdog Timer
11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 11.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3008 chip. This internal reset signal clears OVF to 0, but the WRST bit
remains set to 1. The reset routine must therefore clear the WRST bit.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
WDT internal
reset
WRST
Figure 11.7 Timing of Setting of WRST Bit and Internal Reset
Rev.4.00 Aug. 20, 2007 Page 319 of 638
REJ09B0395-0400