HD6413008VF25 Datasheet, PDF (374/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12. Serial Communication Interface
12.2.5 Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock
source for the baud rate generator.
Bit
Initial value
Read/Write
7
6
5
C/A
CHR
PE
0
0
0
R/W R/W R/W
4
3
2
O/E STOP MP
0
0
0
R/W
R/W R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock select 1/0
These bits select the
baud rate generator's
clock source
Multiprocessor mode
Selects the multiprocessor
function
Stop bit length
Selects the stop bit length
Parity mode
Selects even or odd parity
Parity enable
Selects whether a parity bit is added
Character length
Selects character length in asynchronous mode
Communication mode
Selects asynchronous or synchronous mode
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Communication Mode (C/A)/GSM Mode (GM): The function of this bit differs for the
normal serial communication interface and for the smart card interface. Its function is switched
with the SMIF bit in SCMR.
Rev.4.00 Aug. 20, 2007 Page 328 of 638
REJ09B0395-0400