HD6413008VF25 Datasheet, PDF (363/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

11. Watchdog Timer
11.3 Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
11.3.1 Watchdog Timer Operation
Figure 11.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the H8/3008 is internally reset for a duration of 518 states.
The watchdog reset signal can be externally output from the RESO pin to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR.
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
H'FF
WDT overflow
TCNT count
value
TME set to 1
H'00
Internal
reset signal
Start
OVF = 1
H'00 written
in TCNT
Reset
H'00 written
in TCNT
RESO
518 states
132 states
Figure 11.4 Operation in Watchdog Timer Mode
Rev.4.00 Aug. 20, 2007 Page 317 of 638
REJ09B0395-0400