HD6413008VF25 Datasheet, PDF (279/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Contention between General Register Write and Compare Match: If a compare match occurs
in the T₃ state of a general register write cycle, writing takes priority and the compare match signal
is inhibited. See figure 8.40.
General register write cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal write signal
16TCNT
N
N+1
GR
Compare match signal
N
M
General register write data
Inhibited
Figure 8.40 Contention between General Register Write and Compare Match
Rev.4.00 Aug. 20, 2007 Page 233 of 638
REJ09B0395-0400