HD6413008VF25 Datasheet, PDF (436/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Smart Card Interface
Bit 7
GM
0
1
Description
Normal smart card interface mode operation
• The TEND flag is set 12.5 etu after the beginning of the start bit.
• Clock output on/off control only.
GSM mode smart card interface mode operation
• The TEND flag is set 11.0 etu after the beginning of the start bit.
• Clock output on/off and fixed-high/fixed-low control.
(Initial value)
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 12.2.5,
Serial Mode Register (SMR).
13.2.4 Serial Control Register (SCR)
The function of SCR bits 1 and 0 is modified in smart card interface mode.
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE MPIE TEIE CKE1 CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 12.2.6,
Serial Control Register (SCR).
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7
GM
0
1
Bit 1
CKE1
0
1
Bit 0
CKE0
0
1
0
1
0
1
Description
Internal clock/SCK pin is I/O port
(Initial value)
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at low output
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at high output
Internal clock/SCK pin is clock output
Rev.4.00 Aug. 20, 2007 Page 390 of 638
REJ09B0395-0400