HD6413008VF25 Datasheet, PDF (339/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Programmable Timing Pattern Controller (TPC)
10.2.7 Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP₇ to TP₀) on a bit-by-bit basis.
Bit
Initial value
Read/Write
7
NDER7
0
R/W
6
5
NDER6 NDER5
0
0
R/W R/W
4
3
2
NDER4 NDER3 NDER2
0
0
0
R/W R/W R/W
1
0
NDER1 NDER0
0
0
R/W R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically
transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP₇ to TP₀) on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0
0
1
Description
TPC outputs TP to TP are disabled
7
0
(NDR7 to NDR0 are not transferred to PA₇ to PA₀)
TPC outputs TP₇ to TP₀ are enabled
(NDR7 to NDR0 are transferred to PA to PA )
7
0
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 293 of 638
REJ09B0395-0400