HD6413008VF25 Datasheet, PDF (132/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5. Interrupt Controller
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0—IRQ₅ to IRQ₀ Enable (IRQ5E to IRQ0E): These bits enable or disable
IRQ₅ to IRQ₀ interrupts.
Bits 5 to 0
IRQ5E to IRQ0E Description
0
IRQ₅ to IRQ₀ interrupts are disabled
1
IRQ to IRQ interrupts are enabled
5
0
(Initial value)
5.2.5 IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs
at
pins
IRQ
5
to
IRQ₀.
Bit
Initial value
Read/Write
7
⎯
0
R/W
6
5
4
3
2
1
0
⎯ IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ ₅ to IRQ₀ sense control
These bits select level sensing or falling-edge
sensing for IRQ ₅ to IRQ ₀ interrupts
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or
falling-edge sensing.
Bits 5 to 0—IRQ₅ to IRQ₀ Sense Control (IRQ5SC to IRQ0SC): These bits select whether
interrupts IRQ₅ to IRQ₀ are requested by level sensing of pins IRQ₅ to IRQ₀, or by falling-edge
sensing.
Bits 5 to 0
IRQ5SC to IRQ0SC Description
0
Interrupts
are
requested
when
IRQ
5
to
IRQ
0
inputs
are
low
1
Interrupts are requested by falling-edge input at IRQ to IRQ
5
0
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 86 of 638
REJ09B0395-0400