HD6413008VF25 Datasheet, PDF (507/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

18. Power-Down State
18.2.2 Module Standby Control Register H (MSTCRH)
MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the SCI0, SCI1.
Bit
7
6
5
4
3
2
1
0
PSTOP ⎯
⎯
⎯
⎯
⎯ MSTPH1 MSTPH0
Initial value
0
1
1
1
1
0
0
0
Read/Write
R/W
⎯
⎯
⎯
⎯
R/W
R/W
R/W
Reserved bits
φ clock stop
Enables or disables
output of the system clock
Module standby H1 to H0
These bits select modules
to be placed in standby
MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 7
PSTOP
0
1
Description
System clock output is enabled
System clock output is disabled
(Initial value)
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Reserved: This bit can be written and read.
Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.
Bit 1
MSTPH1
0
1
Description
SCI1 operates normally
SCI1 is in standby state
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 461 of 638
REJ09B0395-0400