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| HD6413008VF25 Datasheet, PDF (330/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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10. Programmable Timing Pattern Controller (TPC)
10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the TPC.
16-bit timer compare match signals
Control logic
PADDR
NDERA
TPMR
PBDDR
NDERB
TPCR
TP15
TP14
TP13
TP12
TP11
TP10
TP 9
TP 8
TP 7
TP 6
TP 5
TP 4
TP 3
TP 2
TP 1
TP 0
Pulse output
pins, group 3
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
Legend:
TPMR: TPC output mode register
TPCR: TPC output control register
NDERB: Next data enable register B
NDERA: Next data enable register A
PBDDR: Port B data direction register
PADDR: Port A data direction register
NDRB: Next data register B
NDRA: Next data register A
PBDR: Port B data register
PADR: Port A data register
PBDR
PADR
NDRB
NDRA
Figure 10.1 TPC Block Diagram
Internal
data bus
Rev.4.00 Aug. 20, 2007 Page 284 of 638
REJ09B0395-0400
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