HD6413008VF25 Datasheet, PDF (506/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

18. Power-Down State
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY
0
1
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms. See table 18.3. Set these bits
according to the operating frequency so that the waiting time will be at least 100 μs.
Bit 6
STS2
0
1
1
1
1
Bit 5
STS1
0
1
0
0
1
1
Bit 4
STS0
0
1
0
1
0
1
0
1
Description
Waiting time = 8,192 states
Waiting time = 16,384 states
Waiting time = 32,768 states
Waiting time = 65,536 states
Waiting time = 131,072 states
Waiting time = 262,144 states
Waiting time = 1,024 states
Illegal setting
(Initial value)
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS₀ to CS₇, AS, RD, HWR, and LWR) are kept as outputs or fixed high, or
placed in the high-impedance state in software standby mode.
Bit 1
SSOE
0
1
Description
In software standby mode, the address bus and bus control signals
are all high-impedance
(Initial value)
In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Rev.4.00 Aug. 20, 2007 Page 460 of 638
REJ09B0395-0400