HD6413008VF25 Datasheet, PDF (515/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Clock
oscillator
RES
18. Power-Down State
STBY
Oscillator
settling time
Reset
exception
handling
Figure 18.2 Hardware Standby Mode Timing
18.6 Module Standby Function
18.6.1 Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (SCI1, SCI0, 16-
bit timer, 8-bit timer, and A/D converter) independently in the power-down state. This standby
function is controlled by bits MSTPH2 to MSTPH0 in MSTCRH and bits MSTPL7 to MSTPL0 in
MSTCRL. When one of these bits is set to 1, the corresponding on-chip supporting module is
placed in standby and halts at the beginning of the next bus cycle after the MSTCR write cycle.
18.6.2 Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is
disabled. Read access always results in H'FF data. Write access is ignored.
18.6.3 Usage Notes
When using the module standby function, note the following points.
On-chip Supporting Module Interrupts: Before setting a module standby bit, first disable
interrupts by that module. When an on-chip supporting module is placed in standby by the module
standby function, its registers are initialized, including registers with interrupt request flags.
Pin States: Pins used by an on-chip supporting module lose their module functions when the
module is placed in module standby. What happens after that depends on the particular pin. For
details, see section 7, I/O Ports. Pins that change from the input to the output state require special
care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data
Rev.4.00 Aug. 20, 2007 Page 469 of 638
REJ09B0395-0400