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HD6413008VF25 Datasheet, PDF (513/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
18. Power-Down State
18.4.4 Sample Application of Software Standby Mode
Figure 18.1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit
is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal.
Clock
oscillator
φ
NMI
NMIEG
SSBY
NMI interrupt
handler
NMIEG = 1
SSBY = 1
Software standby
mode (power-
down state)
SLEEP
instruction
Oscillator
settling time
(tosc2)
NMI exception
handling
Figure 18.1 NMI Timing for Software Standby Mode (Example)
18.4.5 Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output current is not reduced.
Rev.4.00 Aug. 20, 2007 Page 467 of 638
REJ09B0395-0400