HD6413008VF25 Datasheet, PDF (357/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

11. Watchdog Timer
11.1.4 Register Configuration
Table 11.2 summarizes the WDT registers.
Table 11.2 WDT Registers
Address*¹
Write*² Read Name
Abbreviation
H'FFF8C H'FFF8C Timer control/status register
TCSR
H'FFF8D Timer counter
TCNT
H'FFF8E H'FFF8F Reset control/status register
RSTCSR
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
R/W Initial Value
R/(W)*³ H'18
R/W H'00
R/(W)*³ H'3F
11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable and writable up-counter.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: The method for writing to TCNT is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
Rev.4.00 Aug. 20, 2007 Page 311 of 638
REJ09B0395-0400