HD6413008VF25 Datasheet, PDF (332/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Programmable Timing Pattern Controller (TPC)
10.1.4 Register Configuration
Table 10.2 summarizes the TPC registers.
Table 10.2 TPC Registers
Address*¹
Name
Abbreviation R/W
Initial Value
H'EE009
Port A data direction register
PADDR
W
H'00
H'FFFD9
Port A data register
PADR
R/(W)*² H'00
H'EE00A
Port B data direction register
PBDDR
W
H'00
H'FFFDA
Port B data register
PBDR
R/(W)*² H'00
H'FFFA0
TPC output mode register
TPMR
R/W
H'F0
H'FFFA1
TPC output control register
TPCR
R/W
H'FF
H'FFFA2
Next data enable register B
NDERB
R/W
H'00
H'FFFA3
Next data enable register A
NDERA
R/W
H'00
H'FFFA5/
H'FFFA7*³
Next data register A
NDRA
R/W
H'00
H'FFFA4/
H'FFFA6*³
Next data register B
NDRB
R/W
H'00
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFFA5 when the same output trigger is selected for TPC
output groups 0 and 1 by settings in TPCR. When the output triggers are different, the
NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address
of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2
and 3 by settings in TPCR. When the output triggers are different, the NDRB address is
H'FFFA6 for group 2 and H'FFFA4 for group 3.
Rev.4.00 Aug. 20, 2007 Page 286 of 638
REJ09B0395-0400