HD6413008VF25 Datasheet, PDF (234/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Counting
Direction
TCLKA pin
TCLKB pin
Down-Counting
↑
High ↓
Low
Low
↑
High ↓
Up-Counting
Low
↑
↑
High
High ↓
↓
Low
In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2
and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting
mode operations take precedence.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the
compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC
remain effective in phase counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The
FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR
0
1
Description
OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows
OVF is set to 1 in TISRC when 16TCNT2 overflows
(Initial value)
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2
0
1
Description
Channel 2 operates normally
Channel 2 operates in PWM mode
(Initial value)
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA₂ becomes a PWM output pin. The
output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1
PWM1
0
1
Description
Channel 1 operates normally
Channel 1 operates in PWM mode
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 188 of 638
REJ09B0395-0400