HD64F3028F25 Datasheet, PDF (95/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

3.6 Memory Map in Each Operating Mode
Figure 3.1 to 3.2 show a memory maps of the H8/3028 Group. The address space is divided into
eight areas.
The EMC bit in BCR can be read and written to select either of the two memory maps. For details,
see section 6.2.5, Bus Control Register (BCR).
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and on-chip registers differ between the 64-kbyte mode
(mode 6), the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5).
The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8
and @aa:16) also differs.
3.6.1 Note on Reserved Areas
The H8/3028 Group memory map includes reserved areas to which read/write access is prohibited.
Note that normal operation is not guaranteed if the following reserved areas are accessed.
The reserved area in the internal I/O register space.
The H8/3028 Group internal I/O register space includes a reserved area to which access is
prohibited. For details see Appendix B, Internal I/O Registers.
Rev. 2.00, 09/03, page 63 of 890