HD64F3028F25 Datasheet, PDF (27/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11.4.1 Operation of TPC Output Pins ............................................................................. 434
11.4.2 Note on Non-Overlapping Output ........................................................................ 434
Section 12 Watchdog Timer ............................................................................................. 437
12.1 Overview ........................................................................................................................... 437
12.1.1 Features ................................................................................................................ 437
12.1.2 Block Diagram ..................................................................................................... 438
12.1.3 Pin Arrangement .................................................................................................. 438
12.1.4 Register Configuration ......................................................................................... 439
12.2 Register Descriptions......................................................................................................... 439
12.2.1 Timer Counter (TCNT) ........................................................................................ 439
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 440
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 442
12.2.4 Notes on Register Access ..................................................................................... 443
12.3 Operation........................................................................................................................... 445
12.3.1 Watchdog Timer Operation.................................................................................. 445
12.3.2 Interval Timer Operation...................................................................................... 446
12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 446
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)................................... 447
12.4 Interrupts ........................................................................................................................... 448
12.5 Usage Notes....................................................................................................................... 448
Section 13 Serial Communication Interface................................................................. 449
13.1 Overview ........................................................................................................................... 449
13.1.1 Features ................................................................................................................ 449
13.1.2 Block Diagram ..................................................................................................... 451
13.1.3 Input/Output Pins ................................................................................................. 452
13.1.4 Register Configuration ......................................................................................... 453
13.2 Register Descriptions......................................................................................................... 454
13.2.1 Receive Shift Register (RSR)............................................................................... 454
13.2.2 Receive Data Register (RDR) .............................................................................. 454
13.2.3 Transmit Shift Register (TSR) ............................................................................. 455
13.2.4 Transmit Data Register (TDR) ............................................................................. 455
13.2.5 Serial Mode Register (SMR) ................................................................................ 456
13.2.6 Serial Control Register (SCR) .............................................................................. 460
13.2.7 Serial Status Register (SSR)................................................................................. 465
13.2.8 Bit Rate Register (BRR)....................................................................................... 470
13.3 Operation........................................................................................................................... 479
13.3.1 Overview .............................................................................................................. 479
13.3.2 Operation in Asynchronous Mode........................................................................ 481
13.3.3 Multiprocessor Communication ........................................................................... 491
13.3.4 Synchronous Operation ........................................................................................ 498
13.4 SCI Interrupts .................................................................................................................... 506
Rev. 2.00, 09/03, page xxv of xxx