HD64F3028F25 Datasheet, PDF (150/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 5—Address 21 Enable (A21E): Enables PA₆ to be used as the A₂₁ address output pin.
Writing 0 in this bit enables A₂₁ output from PA₆. In modes other than 3, 4, and 5, this bit cannot
be modified and PA₆ has its ordinary port functions.
Bit 5
A21E
0
1
Description
PA6 is the A21 address output pin
PA6 is an input/output pin
(Initial value)
Bit 4—Address 20 Enable (A20E): Enables PA₇ to be used as the A₂₀ address output pin.
Writing 0 in this bit enables A₂₀ output from PA₇. This bit can only be modified in mode 5.
Bit 4
A20E
0
1
Description
PA7 is the A20 address output pin (Initial value when in mode 3 or 4)
PA7 is an input/output pin (Initial value when in mode 1, 2, 5, 6 or 7)
Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
0
1
Description
The bus cannot be released to an external device
BREQ and BACK can be used as input/output pins
The bus can be released to an external device
(Initial value)
6.2.5 Bus Control Register (BCR)
Bit
7
6
5
4
3
2
1
0
ICIS1 ICIS0 BROME BRSTS1 BRSTS0 EMC RDEA WAITE
Initial value
1
1
0
0
0
1
1
0
Read/Write R/W
R/W
R/W
R/W R/W
R/W
R/W
R/W
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
address map, selects the area division unit, and enables or disables WAIT pin input.
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev. 2.00, 09/03, page 118 of 890