HD64F3028F25 Datasheet, PDF (455/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11.2.9 TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
1
1
1
1
1
1
1
1
R/W
R/W R/W
R/W R/W
R/W
R/W R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP₁₅ to TP₁₂)
Group 2 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 2
(TP₁₁ to TP₈)
Group 1 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 1
(TP₇ to TP₄)
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
(TP₃ to TP₀)
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP₁₅ to TP₁₂).
Bit 7
G3CMS1
0
1
Bit 6
G3CMS0
0
1
0
1
Description
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 0
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 1
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 2
TPC output group 3 (TP15 to TP12) is triggered by
compare match in 16-bit timer channel 2
(Initial value)
Rev. 2.00, 09/03, page 423 of 890