HD64F3028F25 Datasheet, PDF (264/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
φ
DREQ
Address
bus
RD
CPU cycle
DMAC cycle
CPU
cycle DMAC cycle
T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
HWR , LWR
Minimum 4 states
Next sampling point
Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
Rev. 2.00, 09/03, page 232 of 890