HD64F3028F25 Datasheet, PDF (26/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10.4.5 Operation with Cascaded Connection .................................................................. 395
10.4.6 Input Capture Setting............................................................................................ 398
10.5 Interrupt............................................................................................................................. 399
10.5.1 Interrupt Sources .................................................................................................. 399
10.5.2 A/D Converter Activation .................................................................................... 400
10.6 8-Bit Timer Application Example ..................................................................................... 400
10.7 Usage Notes....................................................................................................................... 401
10.7.1 Contention between 8TCNT Write and Clear ...................................................... 401
10.7.2 Contention between 8TCNT Write and Increment............................................... 402
10.7.3 Contention between TCOR Write and Compare Match....................................... 403
10.7.4 Contention between TCOR Read and Input Capture ........................................... 404
10.7.5 Contention between Counter Clearing by Input Capture
and Counter Increment ......................................................................................... 405
10.7.6 Contention between TCOR Write and Input Capture........................................... 406
10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)......................................................................................... 407
10.7.8 Contention between Compare Matches A and B.................................................. 408
10.7.9 8TCNT Operation and Internal Clock Source Switchover ................................... 408
Section 11 Programmable Timing Pattern Controller (TPC).................................. 411
11.1 Overview ........................................................................................................................... 411
11.1.1 Features ................................................................................................................ 411
11.1.2 Block Diagram ..................................................................................................... 412
11.1.3 TPC Pins............................................................................................................... 413
11.1.4 Registers ............................................................................................................... 414
11.2 Register Descriptions......................................................................................................... 415
11.2.1 Port A Data Direction Register (PADDR) ........................................................... 415
11.2.2 Port A Data Register (PADR) .............................................................................. 415
11.2.3 Port B Data Direction Register (PBDDR)............................................................ 416
11.2.4 Port B Data Register (PBDR)............................................................................... 416
11.2.5 Next Data Register A (NDRA)............................................................................. 417
11.2.6 Next Data Register B (NDRB) ............................................................................. 419
11.2.7 Next Data Enable Register A (NDERA) .............................................................. 421
11.2.8 Next Data Enable Register B (NDERB)............................................................... 422
11.2.9 TPC Output Control Register (TPCR) ................................................................. 423
11.2.10 TPC Output Mode Register (TPMR) ................................................................... 425
11.3 Operation........................................................................................................................... 427
11.3.1 Overview .............................................................................................................. 427
11.3.2 Output Timing ...................................................................................................... 428
11.3.3 Normal TPC Output ............................................................................................. 429
11.3.4 Non-Overlapping TPC Output ............................................................................. 431
11.3.5 TPC Output Triggering by Input Capture............................................................. 433
11.4 Usage Notes....................................................................................................................... 434
Rev. 2.00, 09/03, page xxiv of xxx