HD64F3028F25 Datasheet, PDF (287/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

P2DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a
transition is made to software standby mode while port 2 is functioning as an input/output port and
a P2DDR bit is set to 1, the corresponding pin maintains its output state.
Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores output data
for Port 2. When port 2 functions as an output port, the value of this register is output. When a bit
in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned. When a
bit in P2DDR is cleared to 0, if port 2 is read the corresponding pin logic level is read.
Bit
Initial value
Read/Write
7
P2₇
0
R/W
6
P2₆
0
R/W
5
P2₅
0
R/W
4
P2₄
0
R/W
3
P2₃
0
R/W
2
P2₂
0
R/W
1
P2₁
0
R/W
0
P2₀
0
R/W
Port 2 data 7 to 0
These bits store data for port 2 pins
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 2 Input Pull-Up MOS Control Register (P2PCR): P2PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 2.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
P2₇PCR P2₆PCR P2₅PCR P2₄PCR P2₃PCR P2₂PCR P2₁PCR P2₀PCR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 input pull-up MOS control 7 to 0
These bits control input pull-up
transistors built into port 2
In modes 5 to 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding
bit in P2PCR is set to 1, the input pull-up transistor is turned on.
P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 2.00, 09/03, page 255 of 890