HD64F3028F25 Datasheet, PDF (265/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
CPU cycle
DMAC cycle
CPU cycle
T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T ₁
φ
DREQ
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 7.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
Rev. 2.00, 09/03, page 233 of 890