HD64F3028F25 Datasheet, PDF (301/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Mode 6 and 7 (Single-Chip Mode): P6₇ functions as the clock output pin (φ) or an input port.
P6₆ to P6₀ function as generic input/output ports. P6₇ is the clock output pin (φ) if the PSTOP bit
in MSTCRH is cleared to 0 (initial value), and an input port if this bit is set to 1. A pin in port 6
becomes an output port if the corresponding bit of P6₆DDR to P6₀DDR is set to 1, and an input
port if this pin is cleared to 0.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. Therefore, if a transition is made to software standby mode while
port 6 is functioning as an input/output port and a P6DDR bit is set to 1, the corresponding pin
maintains its output state.
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data
for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a
value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the
P67 pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be
modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding
bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the
corresponding bit in P6DDR is set to 1.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
P6₇
P6 ₆
P6 ₅
P6 ₄
P6 ₃
P6 ₂
P6 ₁
P6 ₀
1
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W R/W
Port 6 data 7 to 0
These bits store data for port 6 pins
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 2.00, 09/03, page 269 of 890