HD64F3028F25 Datasheet, PDF (828/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

TISRB—Timer Interrupt Status Register B
H'FFF65
16-bit timer (all channels)
Bit:
Initial value:
Read/Write:
7
6
5
4
3
2
1
0
— IMIEB2 IMIEB1 IMIEB0 — IMFB2 IMFB1 IMFB0
1
0
0
0
1
0
0
0
— R/W R/W R/W — R/(W)* R/(W)* R/(W)*
Input capture/compare match flag B0
[Clearing condition]
(Initial value)
0 _{Read IMFB0 when IMFB0=1, then write 0 in IMFB0.}
[Setting conditions]
• TCNT0=GRB0 when GRB0 functions as an output
1 _{compare register.}
• TCNT0 value is transferred to GRB0 by an input capture
signal when GRB0 functions as an input capture register.
Input capture/compare match flag B1
[Clearing condition]
(Initial value)
0 _{Read IMFB1 when IMFB1=1, then write 0 in IMFB1.}
[Setting conditions]
• TCNT1=GRB1 when GRB1 functions as an output
1 _{compare register.}
• TCNT1 value is transferred to GRB1 by an input capture
signal when GRB1 functions as an input capture register.
Input capture/compare match flag B2
[Clearing condition]
(Initial value)
0 _{Read IMFB2 when IMFB2=1, then write 0 in IMFB2.}
[Setting conditions]
• TCNT2=GRB2 when GRB2 functions as an output
1 _{compare register.}
• TCNT2 value is transferred to GRB2 by an input capture
signal when GRB2 functions as an input capture register.
Input capture/compare match interrupt enable B0
0 IMIB0 interrupt requested by IMFB0 flag is disabled
1 IMIB0 interrupt requested by IMFB0 is enabled
(Initial value)
Input capture/compare match interrupt enable B1
0 IMIB1 interrupt requested by IMFB1 flag is disabled
1 IMIB1 interrupt requested by IMFB1 is enabled
(Initial value)
Input capture/compare match interrupt enable B2
0 IMIB2 interrupt requested by IMFB2 flag is disabled
1 IMIB2 interrupt requested by IMFB2 is enabled
(Initial value)
Note: * Only 0 can be written, to clear the flag.
Rev. 2.00, 09/03, page 796 of 890