HD64F3028F25 Datasheet, PDF (393/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

9.6 Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer
operations.
Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T₃ state of
a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 9.37.
16TCNT write cycle
T₁
T₂
T₃
φ
Address bus
16TCNT address
Internal write signal
Counter clear signal
16TCNT
N
H'0000
Figure 9.37 Contention between 16TCNT Write and Clear
Rev. 2.00, 09/03, page 361 of 890