HD64F3028F25 Datasheet, PDF (513/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Table 13.9 SMR and SCR Settings and SCI Clock Source Selection
SMR
Bit 7
C/A
0
1
SCR Setting
Bit 1 Bit 0
CKE1 CKE0 Mode
0
0
Asynchronous
1
mode
1
0
1
0
0
Synchronous
1
mode
1
0
1
SCI Transmit/Receive clock
Clock Source SCK Pin Function
Internal
SCI does not use the SCK pin
Outputs clock with frequency matching the
bit rate
External
Inputs clock with frequency 16 times the bit
rate
Internal
Outputs the serial clock
External
Inputs the serial clock
13.3.2 Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
one or two stop bits. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full-duplex communication
is possible. The transmitter and the receiver are both double-buffered, so data can be written and
read while transmitting and receiving are in progress, enabling continuous transmitting and
receiving.
Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and one or two stop bits (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
Rev. 2.00, 09/03, page 481 of 890