HD64F3028F25 Datasheet, PDF (674/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

20.4.3 Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 20.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies.
External Clock: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time is at least 100 µs.
Table 20.3 Clock Frequency and Waiting Time for Clock to Settle
DIV1 DIV0 STS2 STS1 STS0 Waiting Time 25 MHz 20 MHz 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz
000
0
0
8192 states 0.3
0.4
0.46 0.51 0.65 0.8
1.0
0
0
1
16384 states 0.7
0.8
0.91 1.0
1.3
1.6
2.0
0
1
0
32768 states 1.3
1.6
1.8
2.0
2.7
3.3
4.1
0
1
1
65536 states 2.6
3.3
3.6
4.1
5.5
6.6
8.2^*
1
0
0
131072 states 5.2
6.6
7.3^* 8.2^* 10.9^* 13.1^* 16.4
1
0
1
262144 states 10.5^* 13.1^* 14.6 16.4 21.8 26.2 32.8
1 1 0 1024 states 0.04 0.05 0.057 0.064 0.085 0.10 0.13
111
Illegal setting
010
0
0
8192 states 0.7
0.8
0.91 1.02 1.4
1.6
2.0
0
0
1
16384 states 1.3
1.6
1.8
2.0
2.7
3.3
4.1
0
1
0
32768 states 2.6
3.3
3.6
4.1
5.5
6.6
8.2^*
0
1
1
65536 states 5.2
6.6
7.3^* 8.2^* 10.9^* 13.1^* 16.4
1
0
0
131072 states 10.5^* 13.1^* 14.6 16.4 21.8 26.2 32.8
1 0 1 262144 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5
1 1 0 1024 states 0.08 0.10 0.11 0.13 0.17 0.20 0.26
111
Illegal setting
100
0
0
8192 states 1.3
1.6
1.8
2.0
2.7
3.3
4.1
0
0
1
16384 states 2.6
3.3
3.6
4.1
5.5
6.6
8.2^*
0
1
0
32768 states 5.2
6.6
7.3^* 8.2^* 10.9^* 13.1^* 16.4
0
1
1
65536 states 10.5^* 13.1^* 14.6 16.4 21.8 26.2 32.8
1 0 0 131072 states 21.0 26.2 29.1 32.8 43.7 52.4 65.5
1 0 1 262144 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1
1 1 0 1024 states 0.16 0.20 0.23 0.26 0.34 0.41 0.51
111
Illegal setting
110
0
0
8192 states 2.6
3.3
3.6
4.1
5.5
6.6
8.2^*
0
0
1
16384 states 5.2
6.6
7.3^* 8.2^* 10.9^* 13.1^* 16.4
0
1
0
32768 states 10.5 13.1^* 14.6 16.4 21.8 26.2 32.8
0
1
1
65536 states 21.0^* 26.2 29.1 32.8 43.7 52.4 65.5
1 0 0 131072 states 41.9 52.4 58.3 65.5 87.4 104.9 131.1
1 0 1 262144 states 83.9 104.9 116.5 131.1 174.8 209.7 262.1
1 1 0 1024 states 0.33 0.41 0.46 0.51 0.68 0.82 1.0
111
Illegal setting
6 MHz
1.3
2.7
5.5
10.9^*
21.8
43.7
0.17
2.7
5.5
10.9^*
21.8
43.7
87.4
0.34
5.5
10.9^*
21.8
43.7
87.4
174.8
0.68
10.9^*
21.8
43.7
87.4
174.8
349.5
1.4
4 MHz
2.0
4.1
8.2^*
16.4
32.8
65.5
0.26
4.1
8.2^*
16.4
32.8
65.5
131.1
0.51
8.2^*
16.4
32.8
65.5
131.1
262.1
1.02
16.4^*
32.8
65.5
131.1
262.1
524.3
2.0
2 MHz 1 MHz Unit
4.1
8.2^* ms
8.2^* 16.4
16.4 32.8
32.8 65.5
65.5 131.1
131.1 262.1
0.51 1.0
8.2^* 16.4^* ms
16.4 32.8
32.8 65.5
65.5 131.1
131.1 262.1
262.1 524.3
1.0
2.0
16.4^*
32.8
65.5
131.1
262.1
524.3
2.0
32.8^* ms
65.5
131.1
262.1
524.3
1048.6
4.1
32.8^* 65.5 ms
65.5 131.1
131.1 262.1
262.1 524.3
524.3 1048.6
1048.6 2097.1
4.1
8.2^*
* : Recommended setting
Rev. 2.00, 09/03, page 642 of 890