HD64F3028F25 Datasheet, PDF (661/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Table 19.3 Clock Timing
VCC = 3.0 V to 3.6 V
Item
Symbol Min
Max
Unit
External clock input low
tEXL
pulse width
0.3
0.7
tcyc
60
—
ns
External clock input high
tEXH
pulse width
0.3
0.7
tcyc
60
—
ns
External clock rise time
tEXr
External clock fall time
tEXf
Clock low pulse width
tCL
—
5
ns
—
5
ns
0.4
0.6
tcyc
80
—
ns
Clock high pulse width
tCH
0.4
0.6
tcyc
80
—
ns
External clock output
tDEXT^*
500
—
µs
settling delay time
Note: * tDEXT includes a RES pulse width (tRESW). tRESW = 20 tcyc
Test Conditions
φ ≥ 5 MHz
φ < 5 MHz
φ ≥ 5 MHz
φ < 5 MHz
Figure
19.6
Figure 19.6
φ ≥ 5 MHz Figure
φ < 5 MHz ^21.11
φ ≥ 5 MHz
φ < 5 MHz
Figure 19.7
EXTAL
t_EXH
t_EXL
V_CC × 0.7
0.3 V
t_EXr
t_EXf
Figure 19.6 External Clock Input Timing
V_CC × 0.5
Rev. 2.00, 09/03, page 629 of 890