HD64F3028F25 Datasheet, PDF (398/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T₃ state of a general register read cycle, the value before input capture is read.
See figure 9.42.
General register read cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 9.42 Contention between General Register Read and Input Capture
Rev. 2.00, 09/03, page 366 of 890