HD64F3028F25 Datasheet, PDF (436/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10.7.4 Contention between TCOR Read and Input Capture
If an input capture signal occurs in the T₃ state of a TCOR read cycle, the value before input
capture is read. Figure 10.21 shows the timing in this case.
TCORB read cycle
T1
T2
T3
φ
Address bus
TCORB address
Internal read signal
Input capture signal
TCORB
N
M
Internal data bus
N
Figure 10.21 Contention between TCOR Read and Input Capture
Rev. 2.00, 09/03, page 404 of 890