HD64F3028F25 Datasheet, PDF (187/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Tp1
Tp2
Tr
Tc1
Tc2
φ
A23 to A0
Row
Column
AS
High level
Read access
CSn (RAS)
PB₄/PB₅
(UCAS/LCAS)
RD (WE)
High level
D15 to D0
PB₄/PB₅
(UCAS/LCAS)
Write access
RD (WE)
D15 to D0
Note: n = 2 to 5
Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB)
6.5.8 Wait Control
In a DRAM access cycle, wait states can be inserted (1) between the T_r state and T_c1 state, and (2)
between the T_c1 state and T_c2 state.
Insertion of T_rw Wait State between T_r and T_c1: One T_rw state can be inserted between T_r and
T_c1 by setting the RCW bit to 1 in DRCRB.
Insertion of T_w Wait State(s) between T_c1 and T_c2: When the bit in ASTCR corresponding to an
area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted between the T_c1
state and T_c2 state by means of settings in WCRH and WCRL.
Figure 6.20 shows an example of the timing for wait state insertion.
Rev. 2.00, 09/03, page 155 of 890