HD64F3028F25 Datasheet, PDF (381/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Setup for synchronization
Select synchronization 1
Synchronous preset
Synchronous clear
Write to 16TCNT
Clearing
No
synchronized to this
channel?
2
Yes
Select counter clear source 3 Select counter clear source 4
Start counter
5
Start counter
5
Synchronous preset
Counter clear
Synchronous clear
1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
2. When a value is written in 16TCNT in one of the synchronized channels, the same value is
simultaneously written in 16TCNT in the other channels.
3. Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture.
4. Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously.
5. Set the STR bits in TSTR to 1 to start the synchronized counters.
Figure 9.24 Setup Procedure for Synchronization (Example)
Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA₀, TIOCA₁,
and TIOCA₂. For further information on PWM mode, see section 9.4.4, PWM Mode.
Rev. 2.00, 09/03, page 349 of 890