HD64F3028F25 Datasheet, PDF (699/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Condition
f = 2 M to 25 MHz
Item
Symbol Min
Max
Unit Test Conditions
Bus request setup time
tBRQS
25
—
ns
Figure 21.16
Bus acknowledge delay
tBACD1
—
30
ns
time 1
Bus acknowledge delay
tBACD2
—
30
ns
time 2
Bus-floating time
RAS precharge time
CAS precharge time
Row address hold time
RAS delay time 1
RAS delay time 2
CAS delay time 1
CAS delay time 2
WE delay time
CAS pulse width 1
CAS pulse width 2
CAS pulse width 3
RAS access time
Address access time
CAS access time
WE setup time
WE hold time
Write data setup time
WE write data hold time
CAS setup time 1
CAS setup time 2
CAS hold time
RAS pulse width
Signal rise time (all input
pins except EXTAL)
tBZD
tRP
tCP
tRAH
tRAD1
tRAD2
tCASD1
tCASD2
tWCD
tCAS1
tCAS2
tCAS3
tRAC
tAA
tCAC
tWCS
tWCH
tWDS
tWDH
tCSR1
tCSR2
tCHR
tRAS
tSR
—
30
ns
1.5 tcyc – 25 —
ns
0.5 tcyc – 15 —
ns
0.5 tcyc – 15 —
ns
—
25
ns
—
30
ns
—
25
ns
—
25
ns
—
25
ns
1.5 tcyc – 20 —
ns
1.0 tcyc – 20 —
ns
1.0 tcyc – 20 —
ns
—
2.5 tcyc – 40 ns
—
2.0 tcyc – 50 ns
—
1.5 tcyc – 50 ns
0.5 tcyc – 20 —
ns
0.5 tcyc – 15 —
ns
0.5 tcyc – 20 —
ns
0.5 tcyc – 15 —
ns
0.5 tcyc – 20 —
ns
0.5 tcyc – 15 —
ns
0.5 tcyc – 15 —
ns
1.5 tcyc – 15 —
ns
—
100
ns
Figure 21.17 to
figure 21.19
Figure 21.28
Signal fall time (all input
tSF
—
pins except EXTAL)
100
ns
Note: In order to secure the address hold time relative to the rise of the RD strobe, address
update mode 2 should be used. For details see section 6.3.5, Address Output Method.
Rev. 2.00, 09/03, page 667 of 890