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| HD64F3028F25 Datasheet, PDF (38/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series | |||
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1.2 Block Diagram
Figure 1.1 shows an internal block diagram.
MD 2
MD 1
MD 0
EXTAL
XTAL
STBY
RES
RESO/FWE*
NMI
Ï/P67
LWR/P66
HWR/P65
RD/P64
AS/P63
BACK/P62
BREQ/P61
WAIT/P60
CS0/P84
ADTRG/CS1/IRQ3/P83
CS2/IRQ2/P82
CS3/IRQ1/P81
RFSH/IRQ0/P80
Port 3
Address bus
Data bus (upper)
Data bus (lower)
Port 4
H8/300H CPU
Interrupt controller
ROM
(mask ROM or
flash memory)
DMA controller
(DMAC)
RAM
16-bit timer unit
8-bit timer unit
Programmable
timing pattern
controller (TPC)
Watchdog timer
(WDT)
Serial communication
interface
(SCI) Ã 3 channels
A/D converter
D/A converter
P53 /A 19
P52 /A 18
P51 /A 17
P50 /A 16
P27/A 15
P26/A 14
P25/A 13
P24/A 12
P23/A 11
P22/A 10
P21/A 9
P20/A 8
P17/A 7
P16/A 6
P15/A 5
P14/A 4
P13/A 3
P12/A 2
P11/A 1
P10/A 0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RxD1
P92/RxD0
P91/TxD 1
P90/TxD 0
Port B
Port A
Port 7
Note: * Functions as RESO in mask ROM version and as FWE in flash memory version.
Figure 1.1 Block Diagram
Rev. 2.00, 09/03, page 6 of 890
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