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| HD64F3028F25 Datasheet, PDF (712/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series | |||
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T1
T2
Ï
tAD
A23 to A3
CSn
A2 to A0
AS
RD
tASD
tACC4
tAS1
tASD
tACC4
tAS1
tACC2
D15 to D0
T3
T1
T2
tAD
tSD tAH
tRDS
tASD
tAS1
tSD
tAH
tRSD
tACC1
tRDS
tRDH*
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 21.14 Burst ROM Access Timing: Two-State Access
Rev. 2.00, 09/03, page 680 of 890
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