HD64F3028F25 Datasheet, PDF (157/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 7
MXC1
0
1
Bit 6
MXC0
0
1
0
1
Description
Column address: 8 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5
8-bit access space
16-bit access space
Column address: 9 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5
8-bit access space
16-bit access space
Column address: 10 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5
8-bit access space
16-bit access space
Illegal setting
A19 to A8
A19 to A9
A23 to A8
A23 to A9
A19 to A9
A19 to A10
A23 to A9
A23 to A10
A19 to A10
A19 to A11
A23 to A10
A23 to A11
Bit 5—CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2
to 5 are designated as DRAM space.
Bit 5
CSEL
0
1
Description
PB4 and PB5 selected as UCAS and LCAS output pins
HWR and LWR selected as UCAS and LCAS output pins
(Initial value)
Bit 4—Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle
insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not
inserted regardless of the setting of this bit.
Bit 4
RCYCE
0
1
Description
Refresh cycles disabled
DRAM refresh cycles enabled
(Initial value)
Rev. 2.00, 09/03, page 125 of 890