HD64F3028F25 Datasheet, PDF (837/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

TCSR0—Timer Control/Status Register 0
H'FFF82
8-bit timer channel 0
Bit
7
6
CMFB CMFA
5
OVF
4
ADTE
Initial value
0
0
0
0
Read/Write R/(W)^* R/(W)^* R/(W)^* R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Output select A1 and A0
Bit 1 Bit 0
OS1 OS0
Description
0 No change at compare match A
0
1 0 output at compare match A
0 1 output at compare match A
1
1 Output toggles at compare match A
Output/input capture edge select B3 and B2
ICE in Bit 3 Bit 2
TCSR1 OIS3 OIS2
Description
0 No change at compare match B
0
1 0 output at compare match B
0
0 1 output at compare match B
1
1 Output toggles at compare match B
0 TCORB input capture on rising edge
0
1 TCORB input capture on falling edge
1
0 TCORB input capture on both rising
1
1 ^{and falling edges}
A/D trigger enable (TCSR0 only)
Bit 4
TRGE*
ADTE
Description
0
A/D converter start requests by compare match A
or an external trigger are disabled
0
1
A/D converter start requests by compare match A
or an external trigger are enabled
0 A/D converter start requests by an external trigger are enabled
1
1 A/D converter start requests by compare match A are enabled
Note: * TRGE is bit 7 of the A/D control register (ADCR).
Timer overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
1 ^{[Setting condition]}
TCNT overflows from H'FF to H'00.
Compare match flag A
[Clearing condition]
0 _{Read CMFA when CMFA = 1, then write 0 in CMFA.}
1 ^{[Setting condition]}
TCNT = TCORA
Compare match/input capture flag B
0 ^{[Clearing condition]}
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
1 ^{• TCNT = TCORB}
• The TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev. 2.00, 09/03, page 805 of 890