HD64F3028F25 Datasheet, PDF (420/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination
with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the
input capture input detected edge.
The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
ICE Bit in
8TCSR1
(8TCSR3)
0
1
Bit 3
OIS3
0
1
0
1
Bit 2
OIS2
0
1
0
1
0
1
0
1
Description
No change when compare match B occurs
(Initial value)
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs (toggle output)
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising and falling edges
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
0
1
Bit 0
OS0
0
1
0
1
Description
No change when compare match A occurs
(Initial value)
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A occurs (toggle output)
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Rev. 2.00, 09/03, page 388 of 890