HD64F3028F25 Datasheet, PDF (229/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7.2.4 Data Transfer Control Registers (DTCR)
A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the
operation of one DMAC channel.
Bit
Initial value
Read/Write
7
DTE
0
R/W
6
DTSZ
0
R/W
5
DTID
0
R/W
4
RPE
0
R/W
3
DTIE
0
R/W
2
DTS2
0
R/W
1
DTS1
0
R/W
0
DTS0
0
R/W
Data transfer enable
Enables or disables
data transfer
Data transfer select
These bits select the data
transfer activation source
Data transfer size
Selects byte or
word size
Data transfer interrupt enable
Enables or disables the CPU interrupt
at the end of the transfer
Data transfer
increment/decrement
Selects whether to
increment or decrement
the memory address
register
Repeat enable
Selects repeat
mode
The DTCRs are initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the
DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when
activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not
accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.
Bit 7
DTE
0
1
Description
Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0
when the specified number of transfers have been completed
Data transfer is enabled
(Initial value)
If DTIE is set to 1, a CPU interrupt is requested when DTIE is cleared to 0.
Rev. 2.00, 09/03, page 197 of 890