HD64F3028F25 Datasheet, PDF (799/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

BCR—Bus Control Register
H'EE024
Bus controller
Bit
7
6
5
4
3
2
ICIS1 ICIS0 BROME BRSTS1 BRSTS0 —
Initial value
1
1
0
0
0
1
Read/Write R/W
R/W
R/W
R/W
R/W
—
1
0
RDEA WAITE
1
0
R/W R/W
Wait pin enable
0 WAIT pin wait input is disabled
1 WAIT pin wait input is enabled
Area division unit select
0 Area divisions are as follows:
Area 0: 2 MB Area 4: 1.93 MB
Area 1: 2 MB Area 5: 4 kB
Area 2: 8 MB Area 6: 23.75 kB
Area 3: 2 MB Area 7: 22 B
1 Areas 0 to 7 are the same size
(2 MB)
Burst cycle select 0
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Burst cycle select 1
0 Burst access cycle comprises 2 states
1 Burst access cycle comprises 3 states
Burst ROM enable
0 Area 0 is a basic bus interface area
1 Area 0 is a burst ROM interface area
Idle cycle insertion 0
0 No idle cycle is inserted in case of consecutive external read and write cycles
1 Idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle insertion 1
0 No idle cycle is inserted in case of consecutive external read cycles for different areas
1 Idle cycle is inserted in case of consecutive external read cycles for different areas
Rev. 2.00, 09/03, page 767 of 890