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| HD64F3028F25 Datasheet, PDF (444/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series | |||
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11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the TPC.
16-bit timer compare match signals
Control logic
PADDR
NDERA
TPMR
PBDDR
NDERB
TPCR
TP15
TP14
TP13
TP12
TP 11
TP10
TP 9
TP 8
TP 7
TP 6
TP 5
TP 4
TP 3
TP 2
TP 1
TP 0
Pulse output
pins, group 3
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
Legend
TPMR: TPC output mode register
TPCR: TPC output control register
NDERB: Next data enable register B
NDERA: Next data enable register A
PBDDR: Port B data direction register
PADDR: Port A data direction register
NDRB: Next data register B
NDRA: Next data register A
PBDR: Port B data register
PADR: Port A data register
PBDR
PADR
NDRB
NDRA
Figure 11.1 TPC Block Diagram
Internal
data bus
Rev. 2.00, 09/03, page 412 of 890
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