HD64F3028F25 Datasheet, PDF (359/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

9.2.6 Timer Interrupt Status Register C (TISRC)
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
Bit 7
6
5
4
3
2
1
0
— OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0
Initial value 1
Read/Write —
0
0
0
R/W R/W R/W
1
0
0
0
— R/(W)* R/(W)* R/(W)*
Reserved bit
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
Reserved bit
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
Note: * Only 0 can be written, to clear the flag.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 when OVF2 flag is set to 1.
Bit 6
OVIE2
0
1
Description
OVI2 interrupt requested by OVF2 flag is disabled
OVI2 interrupt requested by OVF2 flag is enabled
(Initial value)
Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the
OVF1 when OVF1 flag is set to 1.
Bit 5
OVIE1
0
1
Description
OVI1 interrupt requested by OVF1 flag is disabled
OVI1 interrupt requested by OVF1 flag is enabled
(Initial value)
Rev. 2.00, 09/03, page 327 of 890