HD64F3028F25 Datasheet, PDF (438/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10.7.6 Contention between TCOR Write and Input Capture
If an input capture signal occurs in the T₃ state of a TCOR write cycle, input capture takes priority
and the write to TCOR is not performed. Figure 10.23 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
Input capture signal
8TCNT
M
TCOR
X
M
Figure 10.23 Contention between TCOR Write and Input Capture
Rev. 2.00, 09/03, page 406 of 890