HD64F3028F25 Datasheet, PDF (435/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10.7.3 Contention between TCOR Write and Compare Match
If a compare match occurs in the T₃ state of a TCOR write cycle, writing takes priority and the
compare match signal is inhibited. Figure 10.20 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
8TCNT
N
N+1
TCOR
N
M
Compare match signal
TCOR write data
Inhibited
Figure 10.20 Contention between TCOR Write and Compare Match
Rev. 2.00, 09/03, page 403 of 890