HD64F3028F25 Datasheet, PDF (22/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6.3.4 Chip Select Signals............................................................................................... 134
6.3.5 Address Output Method ....................................................................................... 135
6.4 Basic Bus Interface............................................................................................................ 137
6.4.1 Overview .............................................................................................................. 137
6.4.2 Data Size and Data Alignment ............................................................................. 137
6.4.3 Valid Strobes ........................................................................................................ 138
6.4.4 Memory Areas...................................................................................................... 139
6.4.5 Basic Bus Control Signal Timing......................................................................... 141
6.4.6 Wait Control......................................................................................................... 148
6.5 DRAM Interface................................................................................................................ 150
6.5.1 Overview .............................................................................................................. 150
6.5.2 DRAM Space and RAS Output Pin Settings........................................................ 150
6.5.3 Address Multiplexing ........................................................................................... 152
6.5.4 Data Bus ............................................................................................................... 152
6.5.5 Pins Used for DRAM Interface ............................................................................ 152
6.5.6 Basic Timing ........................................................................................................ 153
6.5.7 Precharge State Control........................................................................................ 154
6.5.8 Wait Control......................................................................................................... 155
6.5.9 Byte Access Control and CAS Output Pin ........................................................... 156
6.5.10 Burst Operation .................................................................................................... 158
6.5.11 Refresh Control .................................................................................................... 163
6.5.12 Examples of Use................................................................................................... 167
6.5.13 Usage Notes.......................................................................................................... 171
6.6 Interval Timer.................................................................................................................... 174
6.6.1 Operation.............................................................................................................. 174
6.7 Interrupt Sources ............................................................................................................... 178
6.8 Burst ROM Interface ......................................................................................................... 178
6.8.1 Overview .............................................................................................................. 178
6.8.2 Basic Timing ........................................................................................................ 179
6.8.3 Wait Control......................................................................................................... 179
6.9 Idle Cycle .......................................................................................................................... 180
6.9.1 Operation.............................................................................................................. 180
6.9.2 Pin States in Idle Cycle ........................................................................................ 183
6.10 Bus Arbiter ........................................................................................................................ 184
6.10.1 Operation.............................................................................................................. 184
6.11 Register and Pin Input Timing........................................................................................... 187
6.11.1 Register Write Timing.......................................................................................... 187
6.11.2 BREQ Pin Input Timing....................................................................................... 188
Section 7 DMA Controller ................................................................................................ 189
7.1 Overview ........................................................................................................................... 189
7.1.1 Features ................................................................................................................ 189
7.1.2 Block Diagram ..................................................................................................... 190
Rev. 2.00, 09/03, page xx of xxx