HD64F3028F25 Datasheet, PDF (784/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

B.3 Functions
Register abbreviation
Register name
TIER—Timer Interrupt Enable Register
Address to which register
is mapped*
H' 90
Bit
7
6
5
4
3
2
1
0
Initial bit values
ICIAE ICIBE ICICE OCIDE OCIAE OCIBE OVIE —
Initial value 0
0
0
0
0
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W
—
Name of on-chip
supporting module
FRT
Bit numbers
Names of the bits.
Dashes (—) indicate
reserved bits.
Possible types of
access
R Read only
W Write only
R/W Read and write
Timer overflow interrupt enable
0 Interrupt requested by OVF flag is disabled
1 Interrupt requested by OVF flag is enabled
Output compare interrupt B enable
0 Interrupt requested by OCFB flag is disabled
1 Interrupt requested by OCFB flag is enabled
Full name of bit
Output compare interrupt A enable
0 Interrupt requested by OCFA flag is disabled
1 Interrupt requested by OCFA flag is enabled
Input capture interrupt D enable
0 ^{Interrupt requested by ICFD flag is disabled}
1 ^{Interrupt requested by ICFD flag is enabled}
Descriptions of
bit settings
Note: * When the EMC bit in BCR is cleared to 0, addresses of some registers are changed.
Rev. 2.00, 09/03, page 752 of 890